Where does the Z80 processor start executing from?
Strangely I can't find this information anywhere online -- I've thoroughly looked at the datasheet, and I've searched things like "Z80 program counter initial value" -- but I can't find anything!
My question is simply: when the Z80 just turns on, what value does the program counter take? (i.e., what instruction does it start executing from?)
Logically, I'd assume it initialises to 0, but I want to be sure of this.
z80
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
add a comment |
Strangely I can't find this information anywhere online -- I've thoroughly looked at the datasheet, and I've searched things like "Z80 program counter initial value" -- but I can't find anything!
My question is simply: when the Z80 just turns on, what value does the program counter take? (i.e., what instruction does it start executing from?)
Logically, I'd assume it initialises to 0, but I want to be sure of this.
z80
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
IIRC when we ran CP/M on a TRS-80 Model I, it required a hardware mod because there was a 4 k ROM starting at address 0, so the OS couldn't gain control of the hardware.
– Ben Crowell
Mar 28 at 13:37
add a comment |
Strangely I can't find this information anywhere online -- I've thoroughly looked at the datasheet, and I've searched things like "Z80 program counter initial value" -- but I can't find anything!
My question is simply: when the Z80 just turns on, what value does the program counter take? (i.e., what instruction does it start executing from?)
Logically, I'd assume it initialises to 0, but I want to be sure of this.
z80
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
Strangely I can't find this information anywhere online -- I've thoroughly looked at the datasheet, and I've searched things like "Z80 program counter initial value" -- but I can't find anything!
My question is simply: when the Z80 just turns on, what value does the program counter take? (i.e., what instruction does it start executing from?)
Logically, I'd assume it initialises to 0, but I want to be sure of this.
z80
z80
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
asked Mar 27 at 17:48
Jacob GarbyJacob Garby
2356
2356
IIRC when we ran CP/M on a TRS-80 Model I, it required a hardware mod because there was a 4 k ROM starting at address 0, so the OS couldn't gain control of the hardware.
– Ben Crowell
Mar 28 at 13:37
add a comment |
IIRC when we ran CP/M on a TRS-80 Model I, it required a hardware mod because there was a 4 k ROM starting at address 0, so the OS couldn't gain control of the hardware.
– Ben Crowell
Mar 28 at 13:37
IIRC when we ran CP/M on a TRS-80 Model I, it required a hardware mod because there was a 4 k ROM starting at address 0, so the OS couldn't gain control of the hardware.
– Ben Crowell
Mar 28 at 13:37
IIRC when we ran CP/M on a TRS-80 Model I, it required a hardware mod because there was a 4 k ROM starting at address 0, so the OS couldn't gain control of the hardware.
– Ben Crowell
Mar 28 at 13:37
add a comment |
1 Answer
1
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Yes, it starts from Zero - like the Intel 8080, the Z80 descends from.
Excerpt from Zilog's March 1978 Product Specification (datasheet), page 2, Pin Description, here the /RESET signal (emphasis mine):
Input, active low. RESET initializes the CPU as follows:
reset interrupt enable flip-flop, clear PC and registers
I and R and set interrupt to 8080A mode.
Similar the description in the 1977 Z80 Technical Manual (03-0029-01) on page 9.
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
2
Thanks! I actually didn't know that the 8080 started at zero either, but it makes complete sense.
– Jacob Garby
Mar 27 at 17:50
15
@dashnick Many don't just start, but take a vector form a predefined location like 6500 and 6800 start at the vector residing at FFFE/FF, 68k takes the initial PC from Vector 1 (address 4..7). Other do start form some address where the IOC locates a loader record, and so on. Starting from Zero is only one of many ways.
– Raffzahn
Mar 27 at 20:57
10
Intels 8086 employs an interesting combination by starting a offset zero, like 8080/Z80, but in segment FFFF, thus at absolute address FFFF0.
– Raffzahn
Mar 27 at 21:19
4
6502 chip reset starts at a vector found at FFFC. FFFA and FFFE are for interrupts. In other words, reset makes a 6502 doJMP(FFFC). But the 6502 requires 0000-01FF be RAM since those are zero page (basically registers) and the stack.
– Harper
Mar 27 at 23:39
2
PDP-11 starts from a location stored at location 50 (octal), if my memory from 40 years ago is to be trusted, or else a bootstrap program starting at that location. We called it the '50-sequence', and often had to enter it from the console toggle switches.
– user207421
Mar 28 at 3:23
|
show 3 more comments
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Yes, it starts from Zero - like the Intel 8080, the Z80 descends from.
Excerpt from Zilog's March 1978 Product Specification (datasheet), page 2, Pin Description, here the /RESET signal (emphasis mine):
Input, active low. RESET initializes the CPU as follows:
reset interrupt enable flip-flop, clear PC and registers
I and R and set interrupt to 8080A mode.
Similar the description in the 1977 Z80 Technical Manual (03-0029-01) on page 9.
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
2
Thanks! I actually didn't know that the 8080 started at zero either, but it makes complete sense.
– Jacob Garby
Mar 27 at 17:50
15
@dashnick Many don't just start, but take a vector form a predefined location like 6500 and 6800 start at the vector residing at FFFE/FF, 68k takes the initial PC from Vector 1 (address 4..7). Other do start form some address where the IOC locates a loader record, and so on. Starting from Zero is only one of many ways.
– Raffzahn
Mar 27 at 20:57
10
Intels 8086 employs an interesting combination by starting a offset zero, like 8080/Z80, but in segment FFFF, thus at absolute address FFFF0.
– Raffzahn
Mar 27 at 21:19
4
6502 chip reset starts at a vector found at FFFC. FFFA and FFFE are for interrupts. In other words, reset makes a 6502 doJMP(FFFC). But the 6502 requires 0000-01FF be RAM since those are zero page (basically registers) and the stack.
– Harper
Mar 27 at 23:39
2
PDP-11 starts from a location stored at location 50 (octal), if my memory from 40 years ago is to be trusted, or else a bootstrap program starting at that location. We called it the '50-sequence', and often had to enter it from the console toggle switches.
– user207421
Mar 28 at 3:23
|
show 3 more comments
Yes, it starts from Zero - like the Intel 8080, the Z80 descends from.
Excerpt from Zilog's March 1978 Product Specification (datasheet), page 2, Pin Description, here the /RESET signal (emphasis mine):
Input, active low. RESET initializes the CPU as follows:
reset interrupt enable flip-flop, clear PC and registers
I and R and set interrupt to 8080A mode.
Similar the description in the 1977 Z80 Technical Manual (03-0029-01) on page 9.
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
2
Thanks! I actually didn't know that the 8080 started at zero either, but it makes complete sense.
– Jacob Garby
Mar 27 at 17:50
15
@dashnick Many don't just start, but take a vector form a predefined location like 6500 and 6800 start at the vector residing at FFFE/FF, 68k takes the initial PC from Vector 1 (address 4..7). Other do start form some address where the IOC locates a loader record, and so on. Starting from Zero is only one of many ways.
– Raffzahn
Mar 27 at 20:57
10
Intels 8086 employs an interesting combination by starting a offset zero, like 8080/Z80, but in segment FFFF, thus at absolute address FFFF0.
– Raffzahn
Mar 27 at 21:19
4
6502 chip reset starts at a vector found at FFFC. FFFA and FFFE are for interrupts. In other words, reset makes a 6502 doJMP(FFFC). But the 6502 requires 0000-01FF be RAM since those are zero page (basically registers) and the stack.
– Harper
Mar 27 at 23:39
2
PDP-11 starts from a location stored at location 50 (octal), if my memory from 40 years ago is to be trusted, or else a bootstrap program starting at that location. We called it the '50-sequence', and often had to enter it from the console toggle switches.
– user207421
Mar 28 at 3:23
|
show 3 more comments
Yes, it starts from Zero - like the Intel 8080, the Z80 descends from.
Excerpt from Zilog's March 1978 Product Specification (datasheet), page 2, Pin Description, here the /RESET signal (emphasis mine):
Input, active low. RESET initializes the CPU as follows:
reset interrupt enable flip-flop, clear PC and registers
I and R and set interrupt to 8080A mode.
Similar the description in the 1977 Z80 Technical Manual (03-0029-01) on page 9.
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
Yes, it starts from Zero - like the Intel 8080, the Z80 descends from.
Excerpt from Zilog's March 1978 Product Specification (datasheet), page 2, Pin Description, here the /RESET signal (emphasis mine):
Input, active low. RESET initializes the CPU as follows:
reset interrupt enable flip-flop, clear PC and registers
I and R and set interrupt to 8080A mode.
Similar the description in the 1977 Z80 Technical Manual (03-0029-01) on page 9.
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
edited Mar 28 at 7:50
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
answered Mar 27 at 17:49
RaffzahnRaffzahn
55.4k6136224
55.4k6136224
2
Thanks! I actually didn't know that the 8080 started at zero either, but it makes complete sense.
– Jacob Garby
Mar 27 at 17:50
15
@dashnick Many don't just start, but take a vector form a predefined location like 6500 and 6800 start at the vector residing at FFFE/FF, 68k takes the initial PC from Vector 1 (address 4..7). Other do start form some address where the IOC locates a loader record, and so on. Starting from Zero is only one of many ways.
– Raffzahn
Mar 27 at 20:57
10
Intels 8086 employs an interesting combination by starting a offset zero, like 8080/Z80, but in segment FFFF, thus at absolute address FFFF0.
– Raffzahn
Mar 27 at 21:19
4
6502 chip reset starts at a vector found at FFFC. FFFA and FFFE are for interrupts. In other words, reset makes a 6502 doJMP(FFFC). But the 6502 requires 0000-01FF be RAM since those are zero page (basically registers) and the stack.
– Harper
Mar 27 at 23:39
2
PDP-11 starts from a location stored at location 50 (octal), if my memory from 40 years ago is to be trusted, or else a bootstrap program starting at that location. We called it the '50-sequence', and often had to enter it from the console toggle switches.
– user207421
Mar 28 at 3:23
|
show 3 more comments
2
Thanks! I actually didn't know that the 8080 started at zero either, but it makes complete sense.
– Jacob Garby
Mar 27 at 17:50
15
@dashnick Many don't just start, but take a vector form a predefined location like 6500 and 6800 start at the vector residing at FFFE/FF, 68k takes the initial PC from Vector 1 (address 4..7). Other do start form some address where the IOC locates a loader record, and so on. Starting from Zero is only one of many ways.
– Raffzahn
Mar 27 at 20:57
10
Intels 8086 employs an interesting combination by starting a offset zero, like 8080/Z80, but in segment FFFF, thus at absolute address FFFF0.
– Raffzahn
Mar 27 at 21:19
4
6502 chip reset starts at a vector found at FFFC. FFFA and FFFE are for interrupts. In other words, reset makes a 6502 doJMP(FFFC). But the 6502 requires 0000-01FF be RAM since those are zero page (basically registers) and the stack.
– Harper
Mar 27 at 23:39
2
PDP-11 starts from a location stored at location 50 (octal), if my memory from 40 years ago is to be trusted, or else a bootstrap program starting at that location. We called it the '50-sequence', and often had to enter it from the console toggle switches.
– user207421
Mar 28 at 3:23
2
2
Thanks! I actually didn't know that the 8080 started at zero either, but it makes complete sense.
– Jacob Garby
Mar 27 at 17:50
Thanks! I actually didn't know that the 8080 started at zero either, but it makes complete sense.
– Jacob Garby
Mar 27 at 17:50
15
15
@dashnick Many don't just start, but take a vector form a predefined location like 6500 and 6800 start at the vector residing at FFFE/FF, 68k takes the initial PC from Vector 1 (address 4..7). Other do start form some address where the IOC locates a loader record, and so on. Starting from Zero is only one of many ways.
– Raffzahn
Mar 27 at 20:57
@dashnick Many don't just start, but take a vector form a predefined location like 6500 and 6800 start at the vector residing at FFFE/FF, 68k takes the initial PC from Vector 1 (address 4..7). Other do start form some address where the IOC locates a loader record, and so on. Starting from Zero is only one of many ways.
– Raffzahn
Mar 27 at 20:57
10
10
Intels 8086 employs an interesting combination by starting a offset zero, like 8080/Z80, but in segment FFFF, thus at absolute address FFFF0.
– Raffzahn
Mar 27 at 21:19
Intels 8086 employs an interesting combination by starting a offset zero, like 8080/Z80, but in segment FFFF, thus at absolute address FFFF0.
– Raffzahn
Mar 27 at 21:19
4
4
6502 chip reset starts at a vector found at FFFC. FFFA and FFFE are for interrupts. In other words, reset makes a 6502 do
JMP(FFFC). But the 6502 requires 0000-01FF be RAM since those are zero page (basically registers) and the stack.– Harper
Mar 27 at 23:39
6502 chip reset starts at a vector found at FFFC. FFFA and FFFE are for interrupts. In other words, reset makes a 6502 do
JMP(FFFC). But the 6502 requires 0000-01FF be RAM since those are zero page (basically registers) and the stack.– Harper
Mar 27 at 23:39
2
2
PDP-11 starts from a location stored at location 50 (octal), if my memory from 40 years ago is to be trusted, or else a bootstrap program starting at that location. We called it the '50-sequence', and often had to enter it from the console toggle switches.
– user207421
Mar 28 at 3:23
PDP-11 starts from a location stored at location 50 (octal), if my memory from 40 years ago is to be trusted, or else a bootstrap program starting at that location. We called it the '50-sequence', and often had to enter it from the console toggle switches.
– user207421
Mar 28 at 3:23
|
show 3 more comments
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IIRC when we ran CP/M on a TRS-80 Model I, it required a hardware mod because there was a 4 k ROM starting at address 0, so the OS couldn't gain control of the hardware.
– Ben Crowell
Mar 28 at 13:37