Cfrgtkky

This is my first Makefile, and I am can't figure out some of the syntax used. The questions are marked below.

$(BUILD_DIR)/%.o: %.c  $(BUILD_DIR) 

  $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@

1. What is the usage of "$(BUILD_DIR)" in the dependency?


2. What is the meaning of "$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@" in the role?

As with most computer languages the syntax of make cannot be clear if you don't know it. If you are using GNU make the GNU make manual is your friend. In the following explanations I will assume that BUILD_DIR = build and that one of the source files is bar/foo.c.

1. 
   

   $(BUILD_DIR) in the list of prerequisites (dependencies) tells make that the build directory (in which object files are supposed to go) must exist before the recipe is executed; logical. There must be another rule somewhere to create the directory if it does not exist yet. Something like:

   
   
   

   $(BUILD_DIR):
   
       mkdir -p $@
   
   

   
   
   

   But unless you forgot to copy an important character, this dependency is terribly sub-optimal. As the last modification time of a directory changes each time its content changes (files or sub-directories added or removed), it will force the re-compilation of all source files every time the directory changes, which is not what you want. A better dependency would be order-only:

   
   
   

   $(BUILD_DIR)/%.o: %.c | $(BUILD_DIR)
   
   

   
   
   

   that tells make to consider only the existence of $(BUILD_DIR), not its last modification time, when deciding to re-build or not.

   
   


2. 
   

   $(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ is just a combination of make automatic variables and functions.

   
   
   
   
   
   • 
     $< and $@ expand as the first prerequisite (bar/foo.c) and the target (build/bar/foo.o) respectively.
   
   
   • 
     $(<:.c=.lst) replaces .c by .lst in $<: bar/foo.lst.
   
   
   • 
     $(notdir $(<:.c=.lst)) removes the directory part: foo.lst.
   
   
   
   

All in all, for a bar/foo.c source file, and with BUILD_DIR = build, the pattern rule would be equivalent to:

    build/bar/foo.o: bar/foo.c | build

        $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=build/foo.lst bar/foo.c -o build/bar/foo.o

Note that there are two different situations to consider:

1. 
   

   All your source files are in the same directory as the Makefile (no bar/foo.c, just foo.c). Then you can simplify your recipe:

   
   
   

   $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(<:.c=.lst) $< -o $@
   
   

   
   
   

   because the $(notdir...) is useless.

   
   


2. 
   

   Your source files can be in sub-directories (bar/foo.c). Then you need the $(notdir...) in your recipe. But be warned that if you have two source files with the same base name (bar/foo.c and baz/foo.c) you will have a name conflict for $(BUILD_DIR)/foo.lst and your Makefile will not work as expected. Moreover, the order-only prerequisite of the rule should be equivalent to build/bar (or build/baz), not just build. And there should be a rule to create it if needed. If it is your case I suggest to change your pattern rule for:

   
   
   

   $(BUILD_DIR)/%.o: %.c
   
       mkdir -p $(dir $@)
   
       $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
   
   

   
   
   

   There are other solutions (secondary expansion...) but there are a bit too complicated for this already too long answer.