Cfrgtkky

I have two .c files and one .h file which is included in both .c files.

I have make file :

CC=gcc

CFLAGS=-I.



OBJ = hellofunc.o hellomake.o



DEPS := $(OBJ:.o=.d)



-include $(DEPS)



%.o: %.c

     $(CC) $(CFLAGS) -MM -MT $@ -MF $(patsubst %.o,%.d,$@) $<

     $(CC) -c -o $@ $< $(CFLAGS)



hellomake: hellomake.o hellofunc.o

    $(CC) -o $@ $^

I modified hellomake.h header file and then ran above make file. It is compiling only the first file which is assigned to DEPS variable, Which is hellofunc.c

FYI, When i change the order of DEPS variable it is compiling hellomake.o , Seems like make is only picking first file assigned to DEPS variable.
Is there anything wrong in my makefile.. Please help.

As @tripleee noted in the comments, make will by default build the first target it encounters. Since the include files are included directly, as if they were cut-and-pasted in place, the first target in the first .d file (which I'm guessing you'll find to be hellofunc.c) is the first target that make encounters, so that's what make aims to build.

If you move the include line to the end of the file, then the first target in the file will be hellomake, and so that's the target make will attempt to build by default.

Meta remark: if you can, I'd say it's better to avoid this pattern of depending on .d files, and instead aim to express sufficiently many of the dependencies ‘by hand’ directly in the makefile. Doing it this .d way does work (ie, I'm not saying what you're doing is wrong) and appears to be labour-saving, but in my experience it tends to be a little brittle, partly because if you don't have the .d files to hand then you suddenly have zero dependencies. In order to have the .d files to hand, you'll have to check them in to your code repository (you are using a repository, aren't you?), but that will mean they'll frequently be trivially out of date, and... it can turn into a bit of a mess.

EDIT: considered MadScientist's comment and blog post about separate recipe for .d files.

You could tell make how to generate the .d files with a separate rule instead of putting this in another recipe (but see the above mentioned blog post for several reasons for not doing so).

And you should probably tell make that your default goal is hellomake:

.DEFAULT_GOAL := hellomake



CC=gcc

CFLAGS=-I.



OBJ = hellofunc.o hellomake.o



DEPS := $(OBJ:.o=.d)



-include $(DEPS)



%.d: %.c

     $(CC) $(CFLAGS) -MM -MT $@ -MF $@ $<



%.o: %.c

     $(CC) -c -o $@ $< $(CFLAGS)



hellomake: hellomake.o hellofunc.o

    $(CC) -o $@ $^

And it would probably be even better if you were letting make find the source files and deduce the rest:

.DEFAULT_GOAL := hellomake



CC     := gcc

CFLAGS := -I.

SRCS   := $(wildcard *.c)

OBJS   := $(patsubst %.c,%.o,$(SRC))

DEPS   := $(patsubst %.c,%.d,$(SRC))



-include $(DEPS)



%.d: %.c

     $(CC) $(CFLAGS) -MM -MT $@ -MF $@ $<



%.o: %.c

     $(CC) -c -o $@ $< $(CFLAGS)



hellomake: $(OBJS)

    $(CC) -o $@ $^

Finally, following MadScientist's advices, a better, more efficient, less prone to failures solution could be:

.DEFAULT_GOAL := hellomake



CC     := gcc

CFLAGS := -I.

SRCS   := $(wildcard *.c)

OBJS   := $(patsubst %.c,%.o,$(SRC))

DEPS   := $(wildcard $(patsubst %.c,%.d,$(SRC)))



include $(DEPS)



%.o: %.c %.d

    $(CC) -MT $@ -MMD -MP -MF $*.Td $(CFLAGS) -c -o $@ $<

    mv -f $*.Td $*.d && touch $@



hellomake: $(OBJS)

    $(CC) -o $@ $^



%.d: ;

.PRECIOUS: %.d