Use VHDL entity with array ports in a systemverilog testbench in Vivado 2018
I have two entities on a systemverilog testbench. One of them provides several 32 bit vectors and I need to connect them as an array of vectors to the other entity. I created a register on the systemverilog testbench reg [31:0] fifo_D[0:7]; but no matter what permutation of the reg I create I get an error,
ERROR: [VRFC 10-717] formal port array_data of type array_t does not match with actual type reg. In a VHDL package I have type array_t is array (0 to 7) of std_logic_vector(31 downto 0);
Thanks in advance
vhdl simulation system-verilog vivado
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
add a comment |
I have two entities on a systemverilog testbench. One of them provides several 32 bit vectors and I need to connect them as an array of vectors to the other entity. I created a register on the systemverilog testbench reg [31:0] fifo_D[0:7]; but no matter what permutation of the reg I create I get an error,
ERROR: [VRFC 10-717] formal port array_data of type array_t does not match with actual type reg. In a VHDL package I have type array_t is array (0 to 7) of std_logic_vector(31 downto 0);
Thanks in advance
vhdl simulation system-verilog vivado
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
1
This might be a limitation of the tool. Please check the user manual of what types they support between the language boundaries.
– dave_59
Nov 15 at 20:36
I'm still unsure if there is a good way to do this but after spending WAY to much time working on it I finally bit the bullet and made a VHDL wrapper for my VHDL entity and expanded the array out into a huge vector. I replaced the original entity in my systemverilog with the wrapper and its working. This is a band aid as opposed to a solution... if there is a solution.
– flyingblindonarocketcycle
Nov 15 at 21:24
add a comment |
I have two entities on a systemverilog testbench. One of them provides several 32 bit vectors and I need to connect them as an array of vectors to the other entity. I created a register on the systemverilog testbench reg [31:0] fifo_D[0:7]; but no matter what permutation of the reg I create I get an error,
ERROR: [VRFC 10-717] formal port array_data of type array_t does not match with actual type reg. In a VHDL package I have type array_t is array (0 to 7) of std_logic_vector(31 downto 0);
Thanks in advance
vhdl simulation system-verilog vivado
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
I have two entities on a systemverilog testbench. One of them provides several 32 bit vectors and I need to connect them as an array of vectors to the other entity. I created a register on the systemverilog testbench reg [31:0] fifo_D[0:7]; but no matter what permutation of the reg I create I get an error,
ERROR: [VRFC 10-717] formal port array_data of type array_t does not match with actual type reg. In a VHDL package I have type array_t is array (0 to 7) of std_logic_vector(31 downto 0);
Thanks in advance
vhdl simulation system-verilog vivado
vhdl simulation system-verilog vivado
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
asked Nov 15 at 20:01
flyingblindonarocketcycle
92
92
1
This might be a limitation of the tool. Please check the user manual of what types they support between the language boundaries.
– dave_59
Nov 15 at 20:36
I'm still unsure if there is a good way to do this but after spending WAY to much time working on it I finally bit the bullet and made a VHDL wrapper for my VHDL entity and expanded the array out into a huge vector. I replaced the original entity in my systemverilog with the wrapper and its working. This is a band aid as opposed to a solution... if there is a solution.
– flyingblindonarocketcycle
Nov 15 at 21:24
add a comment |
1
This might be a limitation of the tool. Please check the user manual of what types they support between the language boundaries.
– dave_59
Nov 15 at 20:36
I'm still unsure if there is a good way to do this but after spending WAY to much time working on it I finally bit the bullet and made a VHDL wrapper for my VHDL entity and expanded the array out into a huge vector. I replaced the original entity in my systemverilog with the wrapper and its working. This is a band aid as opposed to a solution... if there is a solution.
– flyingblindonarocketcycle
Nov 15 at 21:24
1
1
This might be a limitation of the tool. Please check the user manual of what types they support between the language boundaries.
– dave_59
Nov 15 at 20:36
This might be a limitation of the tool. Please check the user manual of what types they support between the language boundaries.
– dave_59
Nov 15 at 20:36
I'm still unsure if there is a good way to do this but after spending WAY to much time working on it I finally bit the bullet and made a VHDL wrapper for my VHDL entity and expanded the array out into a huge vector. I replaced the original entity in my systemverilog with the wrapper and its working. This is a band aid as opposed to a solution... if there is a solution.
– flyingblindonarocketcycle
Nov 15 at 21:24
I'm still unsure if there is a good way to do this but after spending WAY to much time working on it I finally bit the bullet and made a VHDL wrapper for my VHDL entity and expanded the array out into a huge vector. I replaced the original entity in my systemverilog with the wrapper and its working. This is a band aid as opposed to a solution... if there is a solution.
– flyingblindonarocketcycle
Nov 15 at 21:24
add a comment |
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1
This might be a limitation of the tool. Please check the user manual of what types they support between the language boundaries.
– dave_59
Nov 15 at 20:36
I'm still unsure if there is a good way to do this but after spending WAY to much time working on it I finally bit the bullet and made a VHDL wrapper for my VHDL entity and expanded the array out into a huge vector. I replaced the original entity in my systemverilog with the wrapper and its working. This is a band aid as opposed to a solution... if there is a solution.
– flyingblindonarocketcycle
Nov 15 at 21:24