Verilog always block with no sensitivity list
would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*)? Eg code:
always begin
if (sig_a)begin
@(posedge sig_b); // wait for a sig_b posedge event
@(negedge sig_b); // then wait for a sig_b negedge event
event_true=1;
end
if (event_true)begin
@((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
yes =1;
end
else yes =0;
end
verilog system-verilog hdl
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
add a comment |
would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*)? Eg code:
always begin
if (sig_a)begin
@(posedge sig_b); // wait for a sig_b posedge event
@(negedge sig_b); // then wait for a sig_b negedge event
event_true=1;
end
if (event_true)begin
@((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
yes =1;
end
else yes =0;
end
verilog system-verilog hdl
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
there is no combinatorial logic in your example, and it is not synthesizable.
– Serge
Nov 18 '18 at 15:34
It is unusual to have@(posedge ...)inside analwaysblock.
– toolic
Nov 18 '18 at 15:36
add a comment |
would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*)? Eg code:
always begin
if (sig_a)begin
@(posedge sig_b); // wait for a sig_b posedge event
@(negedge sig_b); // then wait for a sig_b negedge event
event_true=1;
end
if (event_true)begin
@((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
yes =1;
end
else yes =0;
end
verilog system-verilog hdl
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*)? Eg code:
always begin
if (sig_a)begin
@(posedge sig_b); // wait for a sig_b posedge event
@(negedge sig_b); // then wait for a sig_b negedge event
event_true=1;
end
if (event_true)begin
@((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
yes =1;
end
else yes =0;
end
verilog system-verilog hdl
verilog system-verilog hdl
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
asked Nov 18 '18 at 14:54
TheSprintingEngineerTheSprintingEngineer
298
298
there is no combinatorial logic in your example, and it is not synthesizable.
– Serge
Nov 18 '18 at 15:34
It is unusual to have@(posedge ...)inside analwaysblock.
– toolic
Nov 18 '18 at 15:36
add a comment |
there is no combinatorial logic in your example, and it is not synthesizable.
– Serge
Nov 18 '18 at 15:34
It is unusual to have@(posedge ...)inside analwaysblock.
– toolic
Nov 18 '18 at 15:36
there is no combinatorial logic in your example, and it is not synthesizable.
– Serge
Nov 18 '18 at 15:34
there is no combinatorial logic in your example, and it is not synthesizable.
– Serge
Nov 18 '18 at 15:34
It is unusual to have
@(posedge ...) inside an always block.– toolic
Nov 18 '18 at 15:36
It is unusual to have
@(posedge ...) inside an always block.– toolic
Nov 18 '18 at 15:36
add a comment |
1 Answer
1
active
oldest
votes
Synthesis tools require a specific template coding style to synthesize your code. Most only allow a single explicit event control ar the beginning of an always block. Some of the higher-level synthesis tools that do allow multiple event controls only allow multiple occurrences of the same clock edge.
Simulation tools don't have these restrictions and will try to execute whatever legal syntax you can compile. BTW, your @((sig_c==1)&&(sig_a==0)) means wait for the expression to change value, not wait for it to become true. The wait(expr)construct means wait for the expression to become true.
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
Thanks Dave ... but how would aalways begin <some code> endwithout a sensitivity list know at which events to trigger , or will this just infer a combi logic kinda likealways @(*)oralways_combdoes?
– TheSprintingEngineer
Nov 19 '18 at 2:21
1
For combinatorial logic, you must provide a sensitivity list. You do this explicitly usingalwaysor implicitly usingalways @*or always_comb`
– dave_59
Nov 19 '18 at 7:01
add a comment |
Your Answer
StackExchange.ifUsing("editor", function () {
StackExchange.using("externalEditor", function () {
StackExchange.using("snippets", function () {
StackExchange.snippets.init();
});
});
}, "code-snippets");
StackExchange.ready(function() {
var channelOptions = {
tags: "".split(" "),
id: "1"
};
initTagRenderer("".split(" "), "".split(" "), channelOptions);
StackExchange.using("externalEditor", function() {
// Have to fire editor after snippets, if snippets enabled
if (StackExchange.settings.snippets.snippetsEnabled) {
StackExchange.using("snippets", function() {
createEditor();
});
}
else {
createEditor();
}
});
function createEditor() {
StackExchange.prepareEditor({
heartbeatType: 'answer',
autoActivateHeartbeat: false,
convertImagesToLinks: true,
noModals: true,
showLowRepImageUploadWarning: true,
reputationToPostImages: 10,
bindNavPrevention: true,
postfix: "",
imageUploader: {
brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/3.0/"u003ecc by-sa 3.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
allowUrls: true
},
onDemand: true,
discardSelector: ".discard-answer"
,immediatelyShowMarkdownHelp:true
});
}
});
Sign up or log in
StackExchange.ready(function () {
StackExchange.helpers.onClickDraftSave('#login-link');
});
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
StackExchange.ready(
function () {
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fstackoverflow.com%2fquestions%2f53362188%2fverilog-always-block-with-no-sensitivity-list%23new-answer', 'question_page');
}
);
Post as a guest
Required, but never shown
1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
Synthesis tools require a specific template coding style to synthesize your code. Most only allow a single explicit event control ar the beginning of an always block. Some of the higher-level synthesis tools that do allow multiple event controls only allow multiple occurrences of the same clock edge.
Simulation tools don't have these restrictions and will try to execute whatever legal syntax you can compile. BTW, your @((sig_c==1)&&(sig_a==0)) means wait for the expression to change value, not wait for it to become true. The wait(expr)construct means wait for the expression to become true.
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
Thanks Dave ... but how would aalways begin <some code> endwithout a sensitivity list know at which events to trigger , or will this just infer a combi logic kinda likealways @(*)oralways_combdoes?
– TheSprintingEngineer
Nov 19 '18 at 2:21
1
For combinatorial logic, you must provide a sensitivity list. You do this explicitly usingalwaysor implicitly usingalways @*or always_comb`
– dave_59
Nov 19 '18 at 7:01
add a comment |
Synthesis tools require a specific template coding style to synthesize your code. Most only allow a single explicit event control ar the beginning of an always block. Some of the higher-level synthesis tools that do allow multiple event controls only allow multiple occurrences of the same clock edge.
Simulation tools don't have these restrictions and will try to execute whatever legal syntax you can compile. BTW, your @((sig_c==1)&&(sig_a==0)) means wait for the expression to change value, not wait for it to become true. The wait(expr)construct means wait for the expression to become true.
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
Thanks Dave ... but how would aalways begin <some code> endwithout a sensitivity list know at which events to trigger , or will this just infer a combi logic kinda likealways @(*)oralways_combdoes?
– TheSprintingEngineer
Nov 19 '18 at 2:21
1
For combinatorial logic, you must provide a sensitivity list. You do this explicitly usingalwaysor implicitly usingalways @*or always_comb`
– dave_59
Nov 19 '18 at 7:01
add a comment |
Synthesis tools require a specific template coding style to synthesize your code. Most only allow a single explicit event control ar the beginning of an always block. Some of the higher-level synthesis tools that do allow multiple event controls only allow multiple occurrences of the same clock edge.
Simulation tools don't have these restrictions and will try to execute whatever legal syntax you can compile. BTW, your @((sig_c==1)&&(sig_a==0)) means wait for the expression to change value, not wait for it to become true. The wait(expr)construct means wait for the expression to become true.
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
Synthesis tools require a specific template coding style to synthesize your code. Most only allow a single explicit event control ar the beginning of an always block. Some of the higher-level synthesis tools that do allow multiple event controls only allow multiple occurrences of the same clock edge.
Simulation tools don't have these restrictions and will try to execute whatever legal syntax you can compile. BTW, your @((sig_c==1)&&(sig_a==0)) means wait for the expression to change value, not wait for it to become true. The wait(expr)construct means wait for the expression to become true.
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
edited Nov 19 '18 at 19:45
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
answered Nov 18 '18 at 16:01
dave_59dave_59
19.8k21537
19.8k21537
Thanks Dave ... but how would aalways begin <some code> endwithout a sensitivity list know at which events to trigger , or will this just infer a combi logic kinda likealways @(*)oralways_combdoes?
– TheSprintingEngineer
Nov 19 '18 at 2:21
1
For combinatorial logic, you must provide a sensitivity list. You do this explicitly usingalwaysor implicitly usingalways @*or always_comb`
– dave_59
Nov 19 '18 at 7:01
add a comment |
Thanks Dave ... but how would aalways begin <some code> endwithout a sensitivity list know at which events to trigger , or will this just infer a combi logic kinda likealways @(*)oralways_combdoes?
– TheSprintingEngineer
Nov 19 '18 at 2:21
1
For combinatorial logic, you must provide a sensitivity list. You do this explicitly usingalwaysor implicitly usingalways @*or always_comb`
– dave_59
Nov 19 '18 at 7:01
Thanks Dave ... but how would a
always begin <some code> end without a sensitivity list know at which events to trigger , or will this just infer a combi logic kinda like always @(*) or always_comb does?– TheSprintingEngineer
Nov 19 '18 at 2:21
Thanks Dave ... but how would a
always begin <some code> end without a sensitivity list know at which events to trigger , or will this just infer a combi logic kinda like always @(*) or always_comb does?– TheSprintingEngineer
Nov 19 '18 at 2:21
1
1
For combinatorial logic, you must provide a sensitivity list. You do this explicitly using
always or implicitly using always @* or always_comb`– dave_59
Nov 19 '18 at 7:01
For combinatorial logic, you must provide a sensitivity list. You do this explicitly using
always or implicitly using always @* or always_comb`– dave_59
Nov 19 '18 at 7:01
add a comment |
Thanks for contributing an answer to Stack Overflow!
- Please be sure to answer the question. Provide details and share your research!
But avoid …
- Asking for help, clarification, or responding to other answers.
- Making statements based on opinion; back them up with references or personal experience.
To learn more, see our tips on writing great answers.
Sign up or log in
StackExchange.ready(function () {
StackExchange.helpers.onClickDraftSave('#login-link');
});
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
StackExchange.ready(
function () {
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fstackoverflow.com%2fquestions%2f53362188%2fverilog-always-block-with-no-sensitivity-list%23new-answer', 'question_page');
}
);
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function () {
StackExchange.helpers.onClickDraftSave('#login-link');
});
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function () {
StackExchange.helpers.onClickDraftSave('#login-link');
});
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function () {
StackExchange.helpers.onClickDraftSave('#login-link');
});
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
there is no combinatorial logic in your example, and it is not synthesizable.
– Serge
Nov 18 '18 at 15:34
It is unusual to have
@(posedge ...)inside analwaysblock.– toolic
Nov 18 '18 at 15:36